The present invention generally relates to memory devices and methods of operation and testing thereof, and more particularly, to memory devices having temperature sensors used, for example, in temperature compensated self-refresh operations.
Typically, a memory cell of Dynamic Random Access Memory (DRAM) includes one cell transistor and one cell capacitor. In such as DRAM cell, data is written by charging the cell capacitor. However, leakage current may remove the charge stored in the cell capacitor over time, even without read/write operations being performed. For this reason, a refresh operation is typically required. In a typical recharge operation, data is read from the cell capacitor and then rewritten thereto.
A time interval for the refresh operation is referred to as a refresh period (tREFmax). As DRAM capacity increases, the refresh period also typically increases. To prevent data from disappearing due to the length of the refresh period, various attempts have been made to reduce leakage current from cell capacitors. In addition, increasing the refresh period can allow the semiconductor memory device to dissipate less current.
In the case of a mobile device, even when all internal circuits except for a semiconductor memory device are in a turned-off state, a self-refresh current flows through the semiconductor memory device so as to perform a self-refresh operation at every refresh period. Some semiconductor memory devices use a temperature sensor to detect an internal chip temperature, and change the self-refresh period depending on the detected temperature. In this manner, the self-refresh period may be extended. This technique is referred to as a Temperature Compensated Self Refresh (TCSR).
Because the leakage current of a cell capacitor typically is strongly dependent on temperature, the leakage current typically increases rapidly as temperature rises. Conversely, leakage current typically decreases as temperature drops. Using the above-described characteristic, current dissipation may be reduced by maintaining a long refresh period when the temperature sensor detects a low temperature.
A typical conventional temperature sensor used in a semiconductor memory device may include a diode stage and a resistor stage coupled in parallel with the diode stage. Temperature characteristics of the currents flowing through the diode stage and the resistor stage are opposite to each other. Using the opposite temperature characteristics, the temperature sensor detects a predefined temperature by adjusting the resistance such that the currents flowing through the diode stage and the resistor stage are matched.
If the predefined temperature is detected, the temperature sensor outputs a corresponding signal. Because the temperature characteristics of the currents flowing through the diode stage and the resistor stage are used, the temperature sensor may be sensitive to variation of the current characteristics of the resistor stage and the diode stage due to process parameter variation. Therefore, the temperature sensor may operate erroneously. To prevent erroneous operation, the temperature detection characteristics may need to be corrected.
FIG. 1 is a block diagram of a conventional temperature-sensor correcting circuit of a semiconductor memory device. A temperature sensor enabling mode register set (MRS) command TSEMRS is applied to enable a temperature sensor 101. The temperature sensor 101 also receives a temperature compensated self refresh circuit driving voltage VTCSR.
If the temperature sensor 101 is enabled by the temperature sensor enabling MRS command TSEMRS, a correction is performed while the temperature of the semiconductor memory device is increased in a controlled fashion. The number of resistors of the resistor stage used in the temperature sensor 101 is adjusted depending on the temperature of the semiconductor memory device, thereby detecting the predetermined temperature. Then, a correction for process parameters is performed by fuse trimming so as to match with the determined resistance.
The temperature sensor 101 outputs two temperature detection signals ST45 and ST75. The first temperature detection signal ST45 is asserted when the temperature is greater than 45° C., while the second temperature detection signal ST75 is asserted when the temperature is greater than 75° C.
The first and second temperature detection signals ST45 and ST75 output from the temperature sensor 101 can be checked via first and second temperature detection pads PADST45 and PADST75, respectively. While checking the output signals of the temperature sensor 101 through the temperature detection pads PADST45 and PADST75, the temperature sensor 101 may be corrected by fuse trimming, which may be accomplished by applying a trimming address TRIMADDR to the temperature sensor 101. The trimming address TRIMADDR is a signal that is applied for performing the fuse trimming according to the measured characteristics of the temperature sensor 101.
In a real self refresh mode, the first and second temperature detection signals ST45 and ST75 output from the temperature sensor 101 are input to a self refresh period control circuit 102. The self-refresh period control circuit 102 controls a self-refresh period of the semiconductor memory device according to the first and second temperature detection signals ST45 and ST75.
In a conventional correction technique, correction is performed after the temperature sensor enabling MRS command TSEMRS is applied to operate the semiconductor memory device in the MRS mode. Therefore, the operating characteristics of the temperature sensor 101 in the self-refresh mode may not be reflected completely in the correction method. In particular, the operating conditions of the temperature sensor 101 may change due to a difference between the MRS mode and the self-refresh mode. This difference may result in a skew between a trip temperature of the temperature sensor 101 in the fuse trimming mode and a trip temperature of the temperature sensor 101 in the real self-refresh mode. Consequently, the performance of the semiconductor memory device may be degraded.
Accordingly, in order to reduce the difference in the operating characteristics of the temperature sensor due to the different operating modes, the semiconductor memory device may further include a circuit capable of performing the trimming operation of the temperature sensor in an environment similar to real operating conditions. That is, the temperature sensor of the semiconductor memory device may be corrected in an environment similar to that of the real self-refresh mode.
However, a failure mode may arise wherein the first and second temperature detection signals ST45 and ST75 are reversed. As described above, the first and second temperature detection signals ST45 and ST75 may be asserted at temperatures above 45° C. and above 75° C., respectively. If the temperature sensor fails, the second temperature detection signal ST75 may be asserted even when the first temperature detection signal ST45 is in a de-asserted state. Such a reversal phenomenon may be caused by variation of manufacturing process conditions.
Accordingly, a semiconductor memory device in which the reversal phenomenon of the temperature detection signals happens may not be capable of correction, which may cause problems in current characteristics of the semiconductor memory device. As a result, there is a need for circuits and methods that can detect a defective semiconductor memory device and/or interrupt the TCSR function of a defective semiconductor memory device in the presence of such a defect.